Industry Expert Blogs

These days, chip design may seem like an intricately connected jigsaw puzzle, including small, oddly shaped interlocking pieces. Instead of static parts of a puzzle – typically, 300, 500, 750 or 1,000 pieces – spread across a coffee table, a chip under design has loads of dynamic parts located in a variety of directories or sub-directories found on various computers. The focal point is the processor, not the center of a well-known and photographed painting or skyline, as is often the case with puzzles.

Ah, but memories are playing almost as big a role as processors, especially in chips slated for mobile multimedia devices with higher bandwidth and performance, and low-cost and power requirements. That means an engineer’s attention is being drawn away from the processor to an increasingly devilish piece of the design – the DDR memory subsystem that includes the DDR controller, PHY and I/O. The DDR memory subsystem, after all, manages the data traffic flowing to and from the processor and external DDR memory. More than a few engineers have struggled to bring up the DDR interface in a new chip design, followed by weeks calibrating the DDR interface timing. If something’s amiss with the DDR memory subsystem, chances are there will be product failure.

Click here to read more ...