In his wide-ranging technology presentation, Liu highlighted the march to 10nm, where the pace of innovation from IP certification and tools validation to manufacturing is happening much faster.
Liu said he expects 10nm customer tapeouts a year from now (second half of 2015) and risk production in the fourth quarter of next year.
"That's six months earlier than the two-year cadence," he said.
At 10 nm, engineers will enjoy designs that are 2.2X denser and 25 percent faster, while consuming 45 percent less power, according to Cliff Hou, TSMC chief technologist, who presented after Liu.
As far as ecosystem preparation, 35 tools in 11 categories have so far been certified using an ARM Cortex-A15 processor. IP validation, including blocks from Cadence, ARM, Analog Bits, and many others has started six months earlier than normal, Liu noted.
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