Interconnect clock gating cuts SoC energy consumption
The SoC interconnect is one area in which efforts to reduce power consumption need be re-evaluated.
Most efforts to control power consumption in System-on-Chip design are focused on the computational units, such as the CPU and GPU. However, other sections of the chip remain largely untapped for energy conservation measures. SoC designers may put themselves at a market disadvantage if they miss the opportunity to reap game-changing power savings from design measures that may cut overall power by as much as 10%.
The SoC interconnect is one area in which efforts to reduce power consumption need be re-evaluated. In computational units such as the GPU or CPU, clock-gating is one of several measures commonly applied to reduce power consumption, but in other areas of the chip, this may have been overlooked.
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