Industry Expert Blogs

Despite all the innovation in functional verification over the past 10 years, engineers are still struggling with system-level verification for systems on chip (SoCs). It is surprisingly difficult to define actual use cases and generate reusable tests. Cadence plans to make system-level SoC verification much easier with this week's (Dec. 11, 2014) announcement of the Perspec System Verifier, a software-driven verification tool that helps engineers define use cases and generate tests.

Perspec System Verifier is part of the Cadence System Development Suite. It lets users graphically specify system-level verification scenarios that involve use cases, and then generate portable, coverage-driven, constrained-random tests. It is “software driven” because it applies tests through C code running on embedded processor models. Customer experience suggests that Perspec System Verifier can offer a 10X productivity improvement compared to typical manual test development.

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