English
Camera SLVS-EC v.2.0 5.0Gbps / MIPI D-PHY v2-1 4.5Gbps combo Receiver 4-Lane
Industry Expert Blogs
|
Avoiding Redundant Simulation Cycles for your UVM VIP with a Simple Save-Restore StrategyVIP Experts Blog - SynopsysJan. 06, 2015 |
In many verification environments, we reuse the same configuration cycles across different testcases. These cycles may involve writing and reading from different configuration and status registers, loading program memories, and other similar tasks to set up a DUT for its targeted stimulus. In many such environments, the time taken during these configuration cycles is very long. Also, there is a lot of redundancy as verification engineers have to run the same set of verified configuration cycles for different testcases leading to a loss in productivity. This is especially true for complex verification environments with multiple interfaces which require different components to be configured.
