Industry Expert Blogs

“Who Knew?” about verification IP (VIP), was the theme of a recent DeepChip post by John Cooley on December 18. More specifically the article states, “Who knew VIP was big and that Wally had a good piece of it?” We knew.

We knew that ASIC and FPGA design engineers can choose to buy design IP from several alternative sources or build their own, but that does not help with the problem of verification. We knew that you don’t really want to rely on the same source that designed your IP, to test it. We knew that you don’t want to write and maintain bus functional models (BFMs) or more complete VIP for standard protocols. Not that you couldn’t, but why would you if you don’t have to?

We also knew that verification teams want easy-to-use VIP that is built on a standard foundation of SystemVerilog, compliant with a protocol’s specification, and is easily configurable to your implementation. That way it integrates into your verification environment just as easily as if you had built it yourself.

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