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This is the first part of a three part series discussing SystemVerilog interfaces and strategies for dealing with parameterization.

Background

SystemVerilog based verification introduces the concept of interfaces to represent communication between design blocks. In its most elemental form a SystemVerilog interface is just a named bundle of signals that can be communicated through a module port as a single item. Design modules that receive this interface can then access signals through this interface reference. However, higher level functions of interfaces can also provide a more strongly typed communication to better represent the design intent. The following is a subset of the higher order functions that are available in SystemVerilog Interfaces:

• Access rules can be enforced on the signal list through the use of clocking blocks and modports
• Functions and tasks can be used to encapsulate higher order sequencing or access control
• Processes such as initial blocks and always blocks can add functionality
• Continuous assignment statements can also add functionality
• Assertions can ensure proper integration

One very important use of SystemVerilog interfaces is to connect static design elements to dynamic testbench elements. Dynamic testbench elements need access to static design elements in order to sample and drive signals, but reusable testbench elements cannot access static design elements except through a special construct named a virtual interface. Virtual interfaces are interface handles within testbench code that can be assigned with an interface instance. Virtual interfaces are dynamic properties and can be assigned to different interface instances in different testbenches which promotes re-usability.

A common technique for designing reusable design blocks is to use parameters to enable different instances of the design block with unique characteristics. For example, a module could be parameterized to allow the data bus width to be defined when the module is declared and the parameter value is provided. SystemVerilog interfaces also support parameterization, but the use of parameterized interfaces introduces unforeseen complications on the testbench side. In order to be assignment compatible a parameterized virtual interface must be specialized with the same values that the interface instance is specialized with. Unless precautions are taken, this can make for some very ugly testbench code with even uglier use models.

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