Industry Expert Blogs
HiSilicon collaborates with Cadence on DDR4 PHY IP for TSMC 16FFCadence IP Blog - Steven BrownFeb. 03, 2015 |
High-performance and high-speed memory design characterized by low-power operation are requirements for today’s leading edge electronics. Cadence is a leader in providing advanced process node, low-power memory IP. Recent news with Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) and HiSilicon Technologies Co. Ltd highlights our collaboration to meet the needs of industry leaders in this area. This is the first customer to license the Cadence® Denali® DDR4 PHY IP, implemented on the TSMC 16nm FinFET process.
Related Blogs
- Extending Arm Total Design Ecosystem to Accelerate Infrastructure Innovation
- Ecosystem Collaboration Drives New AMBA Specification for Chiplets
- Intel Embraces the RISC-V Ecosystem: Implications as the Other Shoe Drops
- Let's Talk PVT Monitoring: Thermal Issues Associated with Modern SoCs - How Hot is Hot?
- Cadence Ports LPDDR4/DDR4 Combo PHY to TSMC 28HPC to Serve Rapid Adoption in Consumer Products