The big news at the CDNLive Silicon Valley Cadence user conference, held March 10-11, 2015, was the Cadence® Innovus™ Implementation System. This massively parallel IC implementation toolset claims 10X faster turnaround times than existing solutions, and it provides a new placement engine, enhanced concurrent optimization capabilities, and a tight integration with power and timing signoff. A keynote speech by Anirudh Devgan (right), senior vice president for the Digital & Signoff Group at Cadence, gave a first look at Innovus just minutes after the news became public.
Devgan portrayed Innovus as a complete IC implementation platform with “dramatic improvements,” including a 10X improvement in runtime and capacity. What’s really important, he said, is “absolute” runtime, which means how much work you can do in a given period of time. “In 24 hours, we can run one-to-two-million instances or more,” he said. “These used to take five days to do.”
More specifically, Devgan showed how a cell design with 9.3M instances got a 9.7X speedup, while a 3M instance cell design got a 7X speedup. He said that Cadence has applied Innovus to chips in a wide variety of markets (mobile, automotive, networking, others) and continues to see “a massive speedup for different classes of design.”
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