UVM verification methodology & System Verilog have become the de-facto standard for IP level functional verification. At Arrow Devices we have created multiple complete and customizable verification solutions successfully using UVM Verification methodology and SystemVerilog.
During this process of VIP catalog creation,we noticed patterns in commonly occurring problems & solutions. These patterns are opportunities for code reuse.“Design Patterns”is a very widely used paradigm in the software world. It is useful for extending code reuse beyond the standard object oriented programming. Verification methodologies such as UVM heavily rely on object orientation to achieve code reuse. But there are other reuse possibilities that cannot be accomplished by only using object-oriented programming. Hence we created the concept of “VIP Factory”. The VIP Factory is a platform for utilizing design patterns to improve productivity of building verification IP solutions.
In this blog we will define what are “design patterns” and demonstrate how they can be applied in the context of building verification IP solutions. We will use transaction implementation as an example because its widely used and well understood.With this approach we have seen about 3x-6x gains in productivity and it is helping us build the Verification IPs faster, better and cheaper.