English
Voltage Monitor with Digital Output TSMC N5P (Multi-domain supply monitoring)
Industry Expert Blogs
|
Q&A: Breaking Through the Verification Debug BottleneckIndustry Insights Blog - Richard Goering , CadenceApr. 20, 2015 |
The EDA industry provides impressive tools for block-level verification test generation, but has so far produced limited automation for debugging. As a result, debug is becoming a major bottleneck in IC functional verification. Shlomi Uziel, vice president of engineering at the Advanced Verification Solutions Group at Cadence, is among those who believe that a new approach to debug is needed.
In this interview Uziel talks about why debug has become a bottleneck, the challenges customers are experiencing, and the requirements for a better solution.
