Timing closure is a “tortoise” for some system-on-chip (SoC) designers just the way many digital guys call RF design a “black art”. Chip designers often tell horror stories of doing up to 20 back-end physical synthesis place & route (SP&R) iterations with each iteration taking a week or more. “Timing closure”, a largely inefficient process mired with uncertainty, can effectively turn into “timing experimentation” if the factors that delay or prevent timing closure are not addressed in the early stages of the design flow.
Today’s new, larger and more complex SoC designs are developed in even shorter timeframes and increasingly demand higher productivity in each phase of the design cycle. Increasing on-chip interconnect design efficiency has historically been key to the recent reductions in SoC design times because the on-chip network touches every IP on the chip and must adapt as the SoC design changes.
The interconnect fabric is akin to an SoC’s skeleton and nervous system, holding the SoC together and managing its on-chip communications while living in the narrow confines of the floorplan “white space” lanes between IP blocks. Increasing the efficiency of interconnect design automatically increases overall SoC design efficiency. However, as chips have grown in size and the number of IP blocks increased, the interconnect IP has become the major source of long timing paths that must be stretched through congested areas of the SoC. Because of these long paths, the interconnect fabric has become a major source of timing closure issues that until now were only uncovered in the back-end SP&R phases of the chip design process.
Click here to read more ...