To verify an RTL design, you must define a stimulus (i.e. what kind of data should be sent to the DUT).
In any test-bench environment, the driver is responsible for signal activities at the bit level. SystemVerilog in functional verification provide this abstraction. It introduces the concept of TRANSACTION, GENERATOR and CHANNEL. Transaction is the actual data item which is generated by the Generator. It is sent to the driver through the Channel to drive it on the DUT interface.