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Maximizing Debug Visibility in Xilinx UltraScale FPGA-Based PrototypesBreaking the Three Laws - Michael PosnerMay. 25, 2015 |
While the Xilinx UltraScale VU440 FPGA device looks to rocket FPGA-based prototyping forward in respect to ASIC gate capacity is sadly does nothing to help you debug your prototype. If anything it amplifies the engineers debug challenge by enabling huge volumes of RTL to be modeled. The HAPS and ProtoCompiler integrated solution debugging capabilities have revolutionized FPGA-based prototype debug but engineers still want more. Proof of this can be seen below in the contrast between the 2011-2012 and 2013-2014 FPMM survey data. The question asked is to rate the most challenging aspect of FPGA-based prototyping. You can see that the priority on debug increased significantly in the 2013-2014 timeframe over the 2012-2013 range.
This is a long blog but I hope you read to the end as it’s filled with great technical data and a previews of what’s coming in the HAPS next generation systems.
