It's incumbent on IP vendors to deliver higher quality designs that enable a smoother back-end process.
As SoC designers, we are usually insulated from the back-end of the chip design process. We don’t encounter the place and route and timing closure problems that must be resolved by others to turn our front-end logic designs into real chips. Those problems often create challenges that delay our project schedules and prevent us from bringing our chip to market in a timely fashion. To reverse these delays, the industry needs to do a better job of improving the front-end design so it can avoid problems in the back end.
We often develop a floorplan for our SoC design and throw our RTL and net list files over the wall to the back-end integrators who must turn it into real placed gates and macros. Our designs may seem logical, conceptually, but when problems arise in the back end, the common practice is to blame the inadequacy of EDA tools and their users.
As an IP vendor, I say it’s time to stop kicking the EDA dog.
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