With increasing complexity in today’s SoC designs, logic verification is one hurdle that all designers are eager to overcome. A majority of the verification effort is spent on debug. This is because typical SoCs consist of a variety of IPs and interfaces. In cases where data has to flow through multiple interfaces in order to reach its final destination, it becomes extremely hard for design engineers to debug failures. While tracking a data packet through different interfaces is time consuming and cumbersome, engineers will also need to have an in-depth knowledge of each of the interfaces' protocols. This is undesirable as a design engineer, generally, if specialized in just one protocol and does not have a deep understanding of all protocols implemented in the SoC.