Next Thursday, September 17th is TSMC’s ecosystem forum event (OIP – Open Innovation Platform) bringing together the EDA, IP and SoC community to present and discuss solutions to today’s design challenges. http://www.tsmc.com/english/newsEvents/events.htm
This year, I will talk about the concept of “IP subsystems”. Below is the abstract of my talk.
The vision of IP subsystems is now a reality with the ability to integrate specific IP blocks, efficient processors and software into a single subsystem targeting a certain application or protocol. A key design requirement of the subsystem is the ability to support SoC derivatives in multiple process variants such as 16FFC or 28HPC/HPC+. In addition, the components of the IP subsystems including interface, analog, processor and foundation IP must meet the design requirements of the target application. The ability to configure the IP subsystem to the application, while ensuring no adverse interaction, signal and power integrity issues exists between the IP blocks is critical. This has a significant influence on the IP design intent and methodology. This presentation will cover the specification, design, integration and qualificationn challenges and solutions for implementation of IP subsystems for IoT/wearables and automotive applications.
For wearables, the IP subsystem must be designed to work with minimal battery drain, be very low cost, support a rapid wake-up time, and have a consistent power management scheme that supports operation down to 0.6 V, and if necessary, overdrive. The design challenges include meeting protocol requirements, since the signaling amplitude for the USB, DDR and PCI Express interfaces are higher than the core voltrage, and latency. To address this challenge, TSMC offers extended Vt options that allow mixed-mode architectures to solve some of the challenges.
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