Greater productivity, lower power, smaller die size and greater bandwidth await teams that adopt proven methodologies to streamline design in mature geometries.
Are you dreading the day when Moore’s Law comes to a grinding halt? I’m concerned, but I’m not as fatalistic as some.
Here’s why: There are plenty of ways to eke out more scalability in the semiconductor design process through greater efficiency.
SoC design realities make it imperative to re-evaluate mature semiconductor processes for greater efficiencies that yield lower costs, higher performance and shorter time to market. Because scaling to lower geometries won’t yield the same economic or technological benefits that have fueled the semiconductor industry in the past, it’s time to consider what else is possible to sustain innovation and growth.
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