Can agile methodologies typically used in software development bring more efficiency to chip design? For UC Berkeley Professor Borivoje Nikolic, the answer is, why not?
“Twenty years ago, technology people had fun making fun of ITRS predictions,” said Nikolic during his Tuesday morning keynote talk at Cadence’s Mixed-Signal Technology Summit in San Jose. “Nowadays, they have a hard time making the cell as small as predicted. As a result, we have lost one technology generation of scaling over the past couple of years.”
Why is scaling slowing down? For one thing, it’s hard to scale SRAM, which occupies half of a typical die, Nikolic noted. While some might see the end of scaling as a problem, Nikolic sees an opportunity to streamline the development process for complex SoCs—and to make these chips more energy efficient to continue generating performance gains.
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