Without a doubt, there’s plenty of innovation happening in the electronics industry right now. The burning question is, how can engineers continue to accelerate this level of innovation while also achieving power, performance, and area (PPA) targets? That was the key topic addressed by Subramani Kengeri, VP of CMOS Platforms at GLOBALFOUNDRIES, on Thursday, Dec. 10, at Cadence’s Digital Implementation Summit.
“We spend billions of dollars in R&D to get the very best technology from a PPA point of view, but if that is not translated into real product, then we have lost a big chunk of value,” Kengeri told attendees at Cadence San Jose headquarters.
Indeed, scaling is continuing from a technical standpoint – we have visibility today into 5nm. But are we scaling at any cost, and are we doing so at the expense of energy efficiency?
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