For decades, tracing back to the days of Deming, the way to tackle complex engineering problems has been the pareto chart. Charting conditions and their contribution to the problem leads to mitigation priorities.
In the case of SoC power management, the old school pareto chart said the processor core was the biggest power hog and needed to be managed first. The industry developed lower power cores, dynamic voltage and frequency scaling (DVFS), power and clock gating, big.LITTLE clusters, and lower leakage transistors and processes. Power got lower.
But, did it get better? In the world of dark silicon, where there are bazillions of transistors and uncertainty over exactly who is doing exactly what to whom at any given time, it can be very hard to say. (Batterygate, the story of the difference between Apple A9 as fabbed at Samsung and TSMC, is a great example.) Techniques to manage power become increasingly difficult. More importantly, if we look at a typical SoC, the processor core may have several challengers on the new school power consumption pareto chart.
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