The customer develops complex SoCs which are used in state-of-the-art, high-end mobile phones and is a leading patent holder in advanced mobile technologies.
Scope of work:
The customer selected T&VS to perform validation using FPGA-based emulation of their mobile phone SoC.
T&VS Technical Solution:
In order to reduce the complexity and increase the work efficiency, T&VS employees worked at the customer location to elicit, gather and understand the requirement by closely working with the SoC architects.
Fitting the required partial SoC Design into the FPGA Subsystem proved to be a major challenge. Once the RTL was released from the customer, T&VS performed the following tasks
- Understand the customer flow of emulation.
- Write a wrapper for the RTL for FPGA porting.
- Generate FPGA memory compatible with the RTL.
- Write time and clock constraints for synthesizing design.
- Synthesize the design using Synplify premier and analyze the timing of the design.
- Partition the RTL into multiple FPGAs.
- Generate the bit files for all the FPGAs.
- Iterate on the following steps:
- Download bit files to the FPGA boards.
- Run tests and debug failures.
- If required, update RTL and re-generate bit files.
- Validate the SoC design by running software applications on the FPGA.
T&VS deployed one of its experienced staff at the customer location to work closely with the customers.
The project was executed in multiple phases with deliverables being reviewed at the end of each phase.
T&VS were able to discover multiple bugs in the RTL and allowed the customer to validate the SoC design through execution of software. The FPGA platform could then be used for further software development.
- The FPGA emulation helped the customer to meet challenging product release schedules.
- Complex hardware system functionalities were verified in advance of tape-out to secure first time working silicon.
- The FPGA-based software validation reduced the overall product development cycle.
- T&VS completed the project without exceeding the original budget and timescales.