As the transistor scalability slows, and software complexity adds bloat, system designers look to heterogeneous cache coherency as a new way to boost performance, cut power and reduce costs.
System designers, if you’re looking for a cure-all for your scalability anxiety, look elsewhere.
Design engineers today are getting squeezed like never before in their efforts to advance performance, add functionality, cut power consumption and reduce cost.
When transistor scalability was a given in our industry, it’s was no problem to double SoC processing power every couple of years and continually add layers to the software stack to address new requirements. The problem with those two approaches today is that they aren’t as effective as they once were.
Given today’s state of affairs, designers looking to remain competitive will have to examine new ways to achieve their goals beside blindly relying on physics.
Moore’s Law, which was once a seemingly bottomless well, might not have run dry, but it certainly may not be as deep as it used to be. The same can be said about the over-reliance on software to cure all shortcomings in hardware design – it’s no panacea, especially in cost-conscious industries like automotive or mobility, where absorbing higher costs is not an option.
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