Industry Expert Blogs

This is part II of an article covering NetSpeed’s network-on-chip (NoC) offerings. This article dives a little deeper into what a NoC is and how NetSpeed’s network synthesis tool, NocStudio, helps system architects optimize a NoC for their system-on-a-chip (SoC) design.

Traditionally IC designers have used proprietary buses, crossbars and switch fabrics to connect their on-chip IPs. These proprietary architectures are fine for simpler ICs but as SoCs become larger and more heterogeneous in nature and foreign IPs are brought in from various sources it has become increasingly difficult to integrate the design using these fabrics. Additionally, dedicated interconnection between multiple IPs requires more wiring, creating congestion and inflating die sizes while possibly leading to increased power consumption to drive the longer interconnects.

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