Last week Intel held a manufacturing day where they revealed a lot of information about their 10nm process for the first time and information on competitor processes continues to slowly come out as well. I thought it would be useful to summarize what we know now, especially since some of what Intel announced was different than what I previously forecast.
Comparing process density keeps getting more and more complex. Many years ago, node names meant something and were related to real process features. As node names became disconnected from actual process dimensions many of us turned to contacted poly pitch (CPP) multiplied by minimum metal pitch (MMP) as a density metric. Standard cells used in logic design have a height that is related to MMP and a width that is related to CPP. Recently companies have begun to push down the number of tracks and since cell height is the number of tracks multiplied by MMP we need to include tracks in our comparisons. Cell width is also getting more complicated, for example Intel discussed single versus dual dummy gates last week and for a two input NAND gate commonly used in logic designs, the cell width is ~4CPP for a dual dummy gate and ~3CPP for a single dummy gate. As I discussed in a previous article Intel has proposed a metric to try to include these factors but the metric has not been adopted by others yet (they just proposed it last week) and all of the information needed to calculate the Intel metric is not available for companies other than Intel. In spite of this I will present my estimates for this metric based on what I consider to be reasonable assumptions.
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