In 2013 ARM announced the AMBA 5 CHI protocol to provide the performance and scale required for infrastructure applications such as networking and data center. The protocol has been highly successful and has been the foundation for ARM many core systems that are scaling up to 32 or more processors on a single system-on-chip.
Today, ARM is happy to announce a new major revision to the CHI specification (AMBA 5 CHI Issue B), which adds many new capabilities and performance enhancements. These enhancements have been used to improve memory latency and increase data throughput on ARM’s latest generation of IP including: the Cortex-A75 and Cortex-A55 processors, the CoreLink CMN-600 Coherent Mesh Network and the CoreLink DMC-620 Dynamic Memory Controller. Some of the key features and benefits include:
- ARMv8.1-A Large System Extensions
- Far atomic operations enable the interconnect to perform high frequency updates to shared data
- Improved virtualization with extended virtual machine IDs and virtual host extensions for type 2 hypervisors
- Support for up to 52-bit physical address space for more addressable memory in a coherency system
- Performance Extensions and Latency Reduction
- Cache stashing allows accelerators or IO devices to stash critical data within a CPU cache for low latency access
- Direct Data Transfer offers significant latency reduction with fast data path return and memory prefetch
- Enhanced RAS aligning with ARMv8.2-A Architecture
- Adds end-to-end data protection and poison signaling
- Enables common error signaling, logging and reporting for CPUs, interconnects and memory controllers
Click here to read more ...