The PCI-SIG Developers Conference 2017 took place in the Santa Clara, California convention center on June 7-8. Today we will provide conference highlights, observations, and result of the 25-year anniversary dinner quiz. The Synopsys team supporting the exhibition was kept very busy, running five live demos showing the latest in PCIe design and verification solutions. There was a lot of interest and queries from attendees regarding what’s new with PCIe VIP and TestSuite, and easy and effective debug using Verdi integrated protocol analyzer.
Did you know – Gen 5 – Up and Running
PCI-SIG announced the PCIe Gen 5 specification at the conference. Synopsys’ booth had a demo of Gen 5 interface IP displaying link up at Gen 5 speed. In addition to Gen 5, some of the hot topics during the conference were PCIe Gen 4 v0.9, re-timers, lane margining, and easy and effective debug using protocol analyzers.
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