Extensible Processors vs Accelerators – and how RISC-V changes the dynamic
If you were to ask any good designer today what is the best architecture for an SoC that needs to manage complex DSP or high bandwidth traffic demands – you will almost always find the recommendation of using one or more off-the-shelf processors, complimented by hardware accelerators to offload complex processing from the main cores. This solution should give the best power and performance outcome.
The accelerators are usually implemented as standalone RTL blocks connected to the main processor bus, and are optimized to be very efficient on the data types they work with. So on the surface they appear to be the logical choice to deliver optimal power and performance.
BUT, how did this common architecture come about, and is it always the best approach?
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