Industry Expert Blogs

Embedding FPGA technology into SoC designs isn’t really a new idea. In fact, at QuickLogic we’ve been doing it for nearly two decades, starting with our FPGA/hard PCI controller SoC all the way back in 1999. The value proposition was the same then as it is now. Higher levels of integration delivering a higher level of functionality, performance, and design flexibility with lower cost, power consumption, and board space requirements. So why hasn’t eFPGA technology taken off much sooner?

The answer lies fundamentally in the relationship between die costs and development costs. Let’s start with die sizes and costs. Our PCI device in 1999 employed a 0.35 micron process which used 24,650 square microns per logic cell. By 2002, the 180nm process we used for our QuickMIPs device resulted in 9,306 square microns per logic cell – less than half the area for more FPGA capability. Today our latest device, the EOS™ S3 Sensor Processing Platform, includes an even greater level of FPGA capability with a die area of just 961 square microns per logic cell through the use of a 40nm process technology. That’s roughly a factor of 25 reduction in the die area of the eFPGA portion of these devices over the last 18 years.

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