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32-Bit RISC-V Embedded Processor and Subsystem, Maps ARM M-0 to M-4. Optimal PPA,
Industry Expert Blogs
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Leading the Charge: Cadence Announces New Verification IP for UFS 3.0, CoaxPress, and HyperRAMFunctional Verification Blog - Team Specman, CadenceMay. 04, 2018 |
Today, Cadence announced three new VIPs, two of which are industry-firsts! Cadence revealed the first available VIP for CoaXPress for high-speed imaging and the first available VIP for HyperRAM high-speed memory. We also unveiled a new JEDEC Universal Flash Storage 3.0 (UFS) VIP. Together, these three new VIPs allow early-adopters to leap off the starting line in the race to create new, incredible SoCs and IPs incorporating these revolutionary new technologies.
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