Verification and validation are often viewed as quite separate parts of the chip development cycle. One being pre-, the other post-silicon – owned by different teams, and with different, dedicated toolsets supporting them.
More recently, considerable attention has fallen on ways of integrating the two disciplines more tightly. Portable stimulus, for example, is a powerful concept, aiming to allow chip design teams to formulate their verification / validation intent just once, and then use that single specification at any stage of the development cycle. All of the EDA companies are embracing the idea of a verification/validation model that scales end-to-end across the development process: from design, through simulation, emulation and into silicon and system validation. Synopsys calls this the ‘verification continuum’; but as I’ve said, pretty much everyone acknowledges the need and is working to fix it.
Less well recognized is the need to scale the whole process “from top to bottom”: to address systemic complexity. This is about more than the hardware. All silicon runs complex and powerful software (much as we might sometimes wish it to be otherwise!) Today, the process of getting the very best possible performance out of that hardware/software combination is where the rubber hits the road.
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