Industry Expert Blogs

A library of digital standard cells implements both Boolean logic and sequential storage functions. These foundation IPs are used extensively and repeatedly within application specific integrated circuits (ASICs), field programmable arrays (FPGAs), microprocessors and system-on-chip devices (SOCs). The behavior of these cells is affected by temperature and voltage conditions, as well as variability in the manufacture of the silicon die. With advanced nodes and low-power technologies comes the challenge for variation-aware characterization to assure that digital libraries will meet functionality and performance requirements. Depending on the final applications and the degree of replication, standard cells might need to be qualified up to six-sigma.

The classic golden method to achieve reliable characterization has been Monte Carlo through intensive SPICE simulations. However, considering that libraries usually include dozens of types of standard cells that will be derived for different foundries, for different nodes, and for different process flavors, characterization under numerous process/voltage/temperature corners (PVTs) is a huge simulation burden that can take months.

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