As data grows at an accelerating pace, more compute power and bandwidth are required to process this data, driving the need for larger and more complex system on chips (SoCs). This is particularly true at a time when our old friend Moore’s Law has lost a step.
However, as the complexity of SOCs increases, so do the costs to manufacture in leading-edge FinFET geometries. As misery loves company, achieving first-time-right silicon has become more difficult as well. Additionally, there are greater challenges for power scaling and yield. In other words, everything gets harder.
Chip disaggregation, or chiplets, offers an alternative to the traditional monolithic SoC scaling approach. Aggregating multiple chiplets to perform the function of a single monolithic IC de-risks the overall system by reducing complexity and increasing yields.
For applications like artificial intelligence (AI), where there is a “Cambrian explosion” in the number of SoCs and architectural approaches under development, chiplets are an ideal solution. Greater experimentation, and faster time to market are possible when a designer can revise a single chiplet as opposed to having to re-spin an entire SoC.
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