Arm TechCon was successfully held at San Jose Convention Center on 8-10th October, 2019. Synopsys protocol experts were there demonstrating our verification solutions for attendees from a wide spectrum of markets like IoT, mobile, automotive, and consumer.
On Wednesday, Satya Acharya, Sr. Applications Engineer Manager, presented a session on Synopsys’ verification automation solution to generate a scalable and reusable design verification environment to perform functional and performance verification using the Arm Adaptive Traffic Profile for AI/ML-based systems.
AI designs typically require exploring multiple architectures, which in turn require a fast and scalable design verification environment that can be used to manage multiple levels of verification. Current verification environments don’t scale well from the block to SoC level. They lack infrastructure for performance-based verification and are effort-intensive and time consuming to build, along with being inherently error-prone because of the required manual intervention. Therefore, there is a pressing need for automation in the overall SoC verification process. Synopsys verification automation solution combined with Verdi debug comes to your rescue.
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