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Last week was IEDM, the International Electronic Devices Meeting. I will write about that later this week, because last week was also the RISC-V Summit, which was originally scheduled for the week before in the Santa Clara Convention Center, but got pushed out a week and moved to the San Jose Convention Center. IEDM is in San Francisco, so I mostly attended IEDM but I came down to San Jose for much of the first day of the RISC-V Summit. I'll cover that today.

I have been following the RISC-V story since EDPS 2016 in Monterey when I first heard about it. If you don't know what RISC-V is (and you might therefore not know it is pronounced "risk five") then see my posts:

• RISC-V—Instruction Sets Want to Be Free
• RISC-V Summit Preview: Pascal or Linux?

In January this year, in a post titled RISC-V Cores: SweRV and ET-Maxion, I wrote:

"The one-sentence summary of the state of RISC-V is that it is already dominant in academia, and has some traction with the defense industry, too. I doubt any chips will be built in academia that are not RISC-V-based, and it is clear that a lot of ideas for things like hardware security will be prototyped in RISC-V. The big question is how significant it will be in the commercial world."

That's a pretty good summary of what I saw in this year's summit. There is lots of progress in the standardization process, building out the software ecosystem, growing the RISC-V foundation, and more. When Rick O'Connor was running the RISC-V foundation (he's now running the OpenHW Group) he told me that there was a huge funnel of products from big names that hadn't yet been announced. But not a lot that met that description was announced this year, apart from Samsung (see below).

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