Industry Expert Blogs

The Joint Electron Device Engineering Council (JEDEC) has been developing and maintaining DRAM standards for years, defining emerging Memory standards like the DRAM standard. The most recent announcement declares the fifth generation of the DRAM, DDR5, is finally ready for release. The work to define DDR5 began in 2017 with the objective of delivering a standard that could move beyond the DDR4 speed limitations of 16 Gb and 3200 MT/s. The intention was to address new applications around data centers high-end servers for handling AI/ML workloads.

Today, DDR5 comes with a significant increase in Data Rates (3200MT/s to 6400MT/s), Memory interface bandwidth (51.2GB/s) and Density (8Gb to 64Gb). DDR5 technology is enabled with lots of new features related to Performance (More number of Banks, Bank Groups, BL16, Enhanced refresh modes, DFE), Reliability (On die ECC, Data CRC for Reads), Low Power (Write Pattern, Lower voltage levels for VDD/VDDQ/VPP), and Enhanced PHY trainings (CS training, Read training patterns, Internal write levelling, Improved CA training) in order to handle high frequency and accuracy requirements. These features allow up to 30% higher bandwidth even when operating at DDR4 speed.

Click here to read more ...