The latest SoCs on advanced semiconductor nodes typically include a fabric of sensors spread across the die and for good reason. But why and what are the benefits? This first blog of a three-part series explores some of the key applications for In-chip thermal sensing and why embedding in-chip monitoring IP is an essential step to maximise performance and reliability and minimise power, or a combination of these objectives.
The end of Dennard Scaling
As SoC developers migrate to new smaller geometry nodes they enjoy considerable benefits of higher logic density, faster performance and lower power. However, the challenges also increase and need addressing in the light of the objectives to maximise performance, minimize power or optimize reliability or some combination of these, depending on the end application. One of the key challenges is the ‘end of Dennard Scaling’ as highlighted by John Hennessy at the AI hardware summit 2019.
A trend to very large chips
This is referring to the fact that since the mid-2000’s as one migrates from one node to the next, the power per unit silicon area is no longer remaining roughly constant but in fact has been steadily increasing. When combined with a trend to very large chips, even approaching reticle size and the introduction of FinFETs which have more difficult thermal properties through their 3D structure, it doesn’t require much imagination to predict chips can potentially develop hotspots/thermal problems.
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