Chip designers working on advanced nodes typically include a fabric of sensors spread across the die for a number of very specific reasons. In this, the second of a three-part blog series Richard McPartland, Moortec’s Technical Marketing Manager continues to explore some of the key applications and benefits of these types of sensing solutions. In this instalment the focus is In-Die Process Speed Detection and why understanding in-chip process speed detection alongside thermal & supply conditions is essential if you want to maximise performance and power, improve reliability and ultimately reduce costs your cutting-edge design.
Continued migration to new smaller geometry nodes has brought considerable benefits associated with higher logic density, faster performance and lower power. These benefits come hand in hand with a raft of new challenges which also need addressing. In the previous blog entitled Key Applications for In Chip Monitoring…Thermal Sensing, we touched on the “End of Dennard Scaling” as just one of these challenges. (Click HERE to learn more)
Why embedded process speed detection?
Process speed has been increasing with each smaller node and with the move from planar to FinFET but variation between die but also within large die, is now a challenge and can make achieving timing closure a real issue. Process monitors within the scribe lane are useful but too far away to give a complete picture of conditions at critical circuits within the die. For these reasons, SoC developers often embed multiple process monitors close to critical circuit blocks across the die to support techniques to improve power and performance.
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