Industry Expert Blogs

In this first part of a 2-part blog series, we look at defining worst case conditions, focusing specifically on device power.

With great power, comes great responsibility…

With each new technology node especially FinFET, the dynamic conditions within a chip are changing and becoming more complex in terms of process speeds, thermal activity and supply variation. Dennard Scaling brought about the ability for power to be scaled down with each successive node so that power per unit area stayed roughly constant. However, as highlighted by John Hennessy at last year’s AI Hardware summit, since the mid-2000s this is no longer the case and we have seen the steady increase in power density per unit silicon area. Hennessy made the point that with Dennard scaling ending and Moore’s Law slowing down, transistor power and costs were no longer heading in the right direction and there’s no free ride for future performance just from process developments.

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