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Applications in 5G, artificial intelligence, augmented reality/virtual reality, and internet of things are driving the growth and adoption of multi-core systems in new system-on-chip (SoC) design project starts. Increasingly these SoC projects are adopting the open standard RISC-V CPU for a variety of functions in these new designs. The ability to add custom extensions is making RISC-V cores even more attractive to optimize solutions for the target applications. While this was possible with previous CPU cores, the impact on ecosystem compatibility, design schedules for verification and debugging outweighed the benefits.

The open standard of the RISC-V ISA makes it easier because of the tools available that automate a previously labor-intensive undertaking. But before discussing the tools, an examination of the benefits that come from adding custom instructions is in order. Today’s SoC designs are becoming increasingly compute-intensive as applications from edge devices (wearables and smart phones) to the cloud (datacenter accelerators). Devices containing these SoCs are processing ever growing amounts of data. Furthermore, this real-world data is analog—sound, images, motion video, LIDAR, Radar, sonar… and must be converted to digital, analyzed and acted upon. While algorithms in these applications demand large amounts of compute power, the designs are constrained by power and cost. Often it is difficult for a standard CPU to meet all these requirements. If the design calls for a specific task to be accelerated, there needs to be a way to achieve this goal and custom extensions is an effective alternative.

To illustrate the improvement resulting from implementing a custom instruction, consider three typical computational task: Finite impulse response (FIR) Filter, CRC32 (32 bit cyclic redundancy check), and 3DES (Triple Data Encryption Standard) algorithms. The table below shows power and performance boost from adding a custom extension to execute these algorithms. The boost ranges from a 20-fold performance speedup to a 300-fold power savings. The development flow to add custom extensions to achieve these performance gains is made possible by new generation of design automation tools.

For the developer to profile the application, tools such as the RISC-V reference model and Simulator from Imperas Software Ltd. can be used to explore options for optimization and identify candidate instructions that could be accelerated with dedicated hardware. The developer can then use a tool such as the Andes Custom Extension (ACE) to create an instruction to accelerate the target function. Using the Imperas simulation tools, the developer can also share a virtual platform with end developers to jump start software development. Once the designer is satisfied that the custom instructions have achieved the desired performance, the next steps are to implement new RTL using ACE and evaluate the resulting power, performance, and area to ensure these parameters meet the overall system requirements.

To further ensure first time silicon success, the designer can define an on-chip monitoring and analytics infrastructure such as that supplied by UltraSoC (now part of Mentor-Siemens). As designs become more complex, with multiple, heterogeneous functional units sourced from many different third-party suppliers, as well as custom logic designed in-house, this becomes increasingly important. Only with Embedded Analytics can engineers ensure that they are realizing the system-level performance gains expected from the creation of customized processors – and the complex interdependencies created within complex SoCs.

These three companies will be explaining their contribution to the design flow for adding custom extensions to the RISC-V CPU core in a webinar scheduled for September 29 at 8:00 AM Pacific Daylight Time. For more information or to register, please click this link.