Demand for die-to-die and chip-to-chip interfaces has been growing steadily in the past few years due to new applications in cloud/data centers, AI (training and edge applications), and High-Performance Computing (HPC). The demand is driven by the requirements of high throughput, low latency and low power in these applications. Advances in packaging technology are further helping the adoption of heterogeneous systems with chiplets/known-good-die(KGD) assembly to create solutions that require the evolution of a new kind of interface popularly known as “Die-to-Die” interfaces.
Interface Types: Serial vs Parallel Approach
Driven by high-performance networking applications, SerDes has been the primary choice for connecting multiple chips and dies as switches and routers are at the forefront of the bandwidth requirements. For homogenous applications where multiple dies are on the same process nodes, USR/XSR SerDes are widely used to connect and scale the performance. However, this comes with a penalty of higher latency and power for each of the SerDes links as they are primarily PAM-4 based at 56G/112G speeds. The new trend is to connect dies using wider parallel IOs. These IOs are single-ended, similar to HBM and DDR memory technologies, and usually forward the clock to eliminate using power-hungry clock and data recovery circuits. With parallel IOs one can expect almost half the latency and power as compared to SerDes interfaces. There are many consortiums and standards working on parallel IOs such as OpenHBI, BoW, AIB, etc. OpenFive is a proponent of open interfaces and is actively involved in standardization efforts.
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