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Accessing Memory Mapped Registers in CXL 2.0 DevicesVIP Experts Blog - Synopsys
Jun. 03, 2021
CXL 1.1 and CXL 2.0 specification differ in the way memory mapped registers are placed and accessed. The CXL 1.1 specification places memory mapped registers in RCRB (Root Complex Register Block) while the CXL 2.0 specification links memory mapped registers in BAR (Base address ranges) of the device. In this blog we will focus on how to access CXL 2.0 specification memory mapped registers.
Register locator DVSEC (Designated Vendor Specific Extended Capability), available in the configuration space, acts as a link to access memory mapped registers. DVSEC contains register blocks which in-turn contain information of BAR allocated for memory mapped registers like component registers, memory device registers and BAR virtualization registers.