PCI Express® (PCIe®) has been on a tear, doubling the data rate with each new generation in response to the torrid rise in data traffic and the needs of advanced workloads. But raising signaling rates gets harder and harder with each doubling. That’s why with PCIe 6.0, we have some of the most dramatic changes yet seen in the standard to enable the jump to 64 GT/s.
First and foremost among the changes is the shift to PAM4 (“Pulse Amplitude Modulation with four levels”) signaling. PAM4 combines two bits per clock cycle for four amplitude levels (00, 01, 10, 11) vs. PCIe 5.0, and earlier generations, which used NRZ modulation with one bit per clock cycle and two amplitude levels (0, 1).
There are always tradeoffs, however, and the transition to PAM4 signal encoding introduces a significantly higher Bit Error Rate (BER) vs. NRZ. This prompted the adoption of a Forward Error Correction (FEC) mechanism to mitigate the higher error rate inherent in PAM4. PCIe 6.0 adopts an FEC that is sufficiently lightweight to have minimal impact on latency.
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