The first wave of DDR5-based servers sport RDIMMs running at 4800 megatransfers per second (MT/s). This is a 50% increase in data rate over top-end 3200 MT/s DDR4 RDIMMs in previous generation high-performance servers. DDR5 memory incorporates a number of innovations, including Decision Feedback Equalization (DFE) and a new DIMM architecture, which enable that speed grade jump and support future scaling.
DDR5 also supports higher capacity DRAM devices. With DDR5 DIMMs, server and system designers will ultimately be able to use densities of up to 64 Gb in a single-die package (SDP). DDR4 maxes out at 16 Gb DRAM in an SDP. DDR5 supports features like on-die ECC, error transparency mode, post-package repair, and read and write CRC modes to support higher-capacity DRAMs. The impact of higher capacity devices obviously translates to higher capacity RDIMMs. So, while DDR4 RDIMMs can have capacities of up to 64 GB (using SDP), DDR5 SDP-based RDIMMs quadruple that to 256 GB in the future.
In order to achieve higher bandwidth and capacity, while maintaining reliability, availability and serviceability (RAS) features, boot time performance and staying within the desired power envelope, DDR5 requires a “smarter DIMM.” To achieve that, greater intelligence is built into a DDR5 RDIMM through the addition of new and more capable support chips. Two of these are the SPD Hub and Temperature Sensor ICs.
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