Industry Expert Blogs

A self-driving car. A helicopter drone on Mars. A thermostat you can adjust from across the globe. What’ll they think of next? Science fiction writer and futurist, Arthur C. Clark, said that “any sufficiently advanced technology is indistinguishable from magic.” The thing is, it’s not magic. It’s engineering. And there are a lot of challenges to work through to make the proverbial “magic” happen. One of the biggest challenges is the continually encroaching power-performance-and-area (PPA) ceiling in traditional monolithic SoC design. To achieve the next big phase of innovation and break the PPA ceiling, you must design differently. And one trend to help you do just that is multi-die chip design.

A multi-die design consists of individual dies, also called chiplets, that support discrete functions and are assembled together—either side-by-side on 2D or 2.5D packages or vertically stacked in 3D packages. The chiplets could be manufactured on different process nodes in a heterogeneous fashion. Until now, employing a multi-die architecture has been difficult. To do it, early adopters have adapted monolithic chip design methodologies to internally defined design and verification flows and developed their own interface technologies. But to make the marketplace for disaggregated dies truly vibrant—one with plug-and-play-like flexibility and interoperability—industry standards and an ecosystem are essential. Enter the Universal Chiplet Interconnect Express (UCIe) specification that enables customizable, package-level integration of chiplets.

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