Industry Expert Blogs

The chip design industry is going through exciting times. Process nodes with smaller geometries have always enticed chip manufacturers and OEMs, as it helps integrate more functionality over SoC. This reduction in the process nodes has been predicted by Moore's law and achieved through scaling rules as per Dennard's law.

Moore's law held for decades, but with the effective upper bound of clock frequencies, quantum tunneling and interconnects limitations, etc., it is on the deathbed. In addition, as shown in the figure, maximum clock frequency has decreased, and even single-thread performance improvements have slowed considerably.

Click here to read more ...