Simulation and formal verification are two key verification strategies used in today’s SoC design and verification flow. With their unique strengths and weaknesses, simulation and formal verification complement each other in finding corner case bugs and ultimately achieving verification closure and signoff.
Simulation and formal verification are usually done by different design verification and formal teams with their own set of signoff goals. These teams typically do not collaborate closely because formal verification and simulation can require different expertise and skillsets. However, there are synergies between simulation and formal that can greatly benefit the overall verification effort and accelerate coverage closure. In this blog, we will examine some of the technology connections between simulation and formal so that verification and formal teams can work together to incorporate both technologies effectively and efficiently to achieve verification signoff.
Why Achieving Coverage Closure is Challenging
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