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To deliver your IP hardware project, you will need a hardware verification campaign that systematically executes verification workloads against a comprehensive verification plan. How do you reach those goals with the shortest time, and the lowest cost, while delivering the highest possible quality? These are the long-established challenges of hardware verification.

Hardware verification engineers are familiar with a range of day-to-day challenges. Over the years, the EDA industry and engineering communities together have evolved effective verification workflows and strategies to address these challenges that enable them to deliver high-quality results within time and cost budgets. But the challenge to deliver quality-of-results (QOR) within both time-to-results (TTR) and cost-of-results (COR) targets is becoming ever harder to meet thanks to exponential complexity and chip design size growth, matched by compute and storage demands that push the successful delivery of complex products out of reach for smaller and some medium-sized hardware IP developers. The dominating cost is tied to hardware verification, with simulation being the dominant hardware verification workflow.

In this article, I’ll explore these challenges and then illustrate how a cloud-based hardware verification flow can help you manage key aspects of the process.

What are the challenges involved in a switch to the cloud as the main execution platform for these highly compute-intensive workflows? What are the key capabilities that must be supported in a cloud environment and what are the new opportunities that arise from that transition? How do you exploit those to improve QOR while reducing TTR and COR?

Let’s start by considering where hardware IP verification engineers spend most of their engineering time and effort. How productive is this and does the cloud both enable and enhance the experience?

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