Industry Expert Blogs

Achieving predictable chip design closure has become progressively challenging for teams worldwide. While linting tools have existed for decades, traditional tools require significant effort to filter out the noise and eventually zero-in on the real design issues. With increasing application specific integrated circuit (ASIC) size and complexity, chip designers require higher debug efficiency when managing a large number of violations in order to ultimately achieve a shorter turnaround time (TAT).

In the first two parts of this linting series, we established how linting offers a comprehensive mechanism to check for fundamental chip design faults and touched on the many benefits of having a guiding methodology for deeper functional lint analysis.

Recognizing the disparities between in-house coding styles, our extensive experience of working with industry leaders has given us an edge to accelerate RTL and system-on-chip (SoC) design flow for customers previously unseen. Solutions such as Synopsys VC SpyGlass™ CDC have already proven how valuable advanced machine learning (ML) algorithms are to achieve SoC design signoff with scalable performance and high debug productivity. Leveraging industry-standard practices and our decades of expertise, the latest offering of Synopsys VC SpyGlass Lint now includes powerful ML capabilities to significantly improve debug efficiency for designers.

In the finale of this blog series, we’ll cover the downside of traditional linting tools, how the functionality of ML and root-cause analysis (ML-RCA) accelerate design signoff, the key benefits of Synopsys VC SpyGlass Lint, and where we see the future of smart linting headed.

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