Industry Expert Blogs

As system designers seek to pack ever-more transistors into smaller spaces, monolithic system-on-chips (SoCs) are quickly nearing the reticle ceiling for manufacturing. Simply put, conventional SoCs are becoming too big and costly to produce, especially for compute-intensive applications such as machine learning (ML), high-performance computing (HPC), and advanced driver assistance systems (ADAS).

Indeed, these workloads are incredibly demanding due to massive parallelism requirements for multiply-accumulate (MAC) operations such as dot product functions. Thanks to multi-die systems, purpose-built chips can now support compute-intensive tasks with a diverse lineup of high-end processors, sophisticated memory arrays, and reliable real-time data connectivity between dies.

Consisting of multiple heterogeneous dies integrated into a single package, multi-die systems offer semiconductor companies a more revolutionary way of designing and fabricating a new generation of silicon. “To be able to tackle these very large workloads, we need to put more silicon in the package than would fit in a single monolithic die,” Gerry Talbot, AMD corporate fellow, explains in a recent MIT Technology Review Insights report. “You physically could not print it in a single reticle.”

Titled “Multi-Die Systems Define the Future of Semiconductors,” the MIT Technology Review report explores why multi-die systems will be instrumental in meeting burgeoning industry demand for compute power. In this blog post, we summarize key sections of the MIT Technology Review report and highlight additional quotes from senior Synopsys executives and industry experts—with a focus on how semiconductor companies can leverage the advances of multi-die systems to create new business opportunities.

Why Multi-Die Systems?

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